The present invention relates generally to the packaging of integrated circuits. More particularly, the invention relates to methods and apparatuses for packaging integrated circuits using a carrier that supports a multiplicity of dies and packaged integrated circuits formed therefrom.
Packaging semiconductors is a vital aspect of semiconductor manufacturing. Although there are many types of packaging configurations available, many improvements are still needed to simplify the package fabrication process. By way of example, many of today's packaging techniques are accomplished by packaging one integrated circuit chip at a time. As a consequence, manufacturing resources are inefficiently utilized which unfortunately has a direct correlation to increased packaging costs.
Another problem with current technology packaging configurations is size. For years there has been a growing demand to miniaturize integrated circuit chips. Although there have been many advancements which have generated smaller integrated circuit chips, the reduction in chip packaging has lagged behind.
An example of a well known packaging technique is shown in FIG. 1A. FIG. 1A shows an integrated circuit chip package 100 having a die 104 mounted on a conventional die attach pad 102. After die 104 is secured to die attach pad 102, a wire bonder is used to interconnect a plurality of wire bonds 106 between die 104 and a plurality of leadframe leads 110. For ease of illustration, only two leads and wire bonds are shown, but as is well known in the art, many more leads 110 and wire bonds 106 are used to provide appropriate die-to-lead interconnection. Once the appropriate interconnections are in place, the entire die and interconnections are encased in an encapsulating material 108. Typical encasing processes include injecting encapsulating material 108 (e.g., molten plastic) into a transfer mold.
As can be appreciated, the overall size of integrated circuit chip package 100 is substantially larger than die 104. In addition, the required fabrication processes involved in serially packaging each integrated circuit chip may be relatively time consuming when large quantities are desired.
In another example, FIGS. 1B-1D illustrate one type of hermetically sealed integrated circuit chip package. Referring first to FIG. 1B, an integrated circuit chip package 120 is shown in a cross-sectional view. The integrated circuit chip package 120 includes a multi-leveled base portion 124 and a lid portion 122. Attached to base portion 124 is a die 104, which is typically affixed to a die attach pad 105. Conventional methods of attaching die 104 include, for example, adhesive epoxies. Once die 104 is attached, a plurality of bonding wires 106 provide electrical connection between die 104 and a plurality of bonding shelves 107. From bonding shelves 107, a conductive lead provides the necessary connection to a plurality of castellations 128. Castellations 128 are defined by conductive half cylindrical surfaces and are formed around base portion 124.
FIG. 1C is a side view of integrated circuit chip package 120 after lid portion 122 has been hermetically sealed to base portion 124. As mentioned above, castellations 128 are conductive half cylindrical surfaces, and are designed to provide electrical interconnection to a bottom portion 127. FIG. 1D is a bottom view of integrated circuit chip package 120 having a plurality of contacts 132. Each contact 132 is coupled to an associated castellation 128.
Although integrated circuit chip package 120 eliminates the need for leads 110 of FIG. 1A, and reduces overall package size, the packaging size (e.g., vertical height) is still substantially larger than appropriate for some applications. A further disadvantage with fabricating multi-level integrated circuit packaging structures (i.e., different levels for a die attach pad, a bond pad and a lid) is the need for additional fabrication equipment to generate each level. Consequently, fabricating large quantities of multi-level integrated circuits may be far more expensive as compared to the benefits obtained from reducing the packaging size.
Another type of integrated circuit packaging is called a chip scale package (CSP). This type of packaging is called a CSP since the size of the package is about size the integrated circuit chip (e.g., die). Currently, there are a wide variety of CSPs available, although most require multiple package levels. Examples include a mini-Ball Grid Array (BGA), and a micro-Ball Grid Array (.mu.BGA).
For illustration purposes, FIG. 1E shows a simplified CSP grid array (GA) package 140 having a dielectric interposer 144 and an integrated circuit chip die 104 that is about the size of the package 140. Between integrated circuit chip die 104 and interposer 144 is an underfill epoxy 142. In this example, the appropriate electrical interconnections between integrated circuit chip 104 and an array of solder balls 146 is made through a number of electrical traces (not shown) constructed through underfill epoxy 142. Although CSP GA designs have been successful in decreasing packaging size, each multi-level integrated circuit must still be packaged individually. Therefore, mass producing GAs tends to be expensive, time consuming and require additional fabrication steps.
In view of the foregoing, there is a need for low cost integrated circuit chip packages that can be fabricated using conventional fabrication equipment and can be mass produced without consuming too many resources to be cost effective.